Hologram

Hologram is a compile-first library that acts as a virtual high-performance hypervisor for computation. It is compiled into your application and runs in-process (same PID and memory space), virtualizing execution across CPU, GPU, and WASM backends.

Hologram transforms byte-level iterative computation into
fused circuit in-memory lookup that execute in constant time O(1).

1. Compile Once

At build time, Hologram analyzes your data, graphs, or models and projects them into a geometric compute space.

Geometric Projection

Byte-level operations are mapped from linear memory into a finite torus representation defined by the Atlas algebraic framework. Each operation compiles to a 96 byte class map, enabling deterministic constant time lookup via geometric canonicalization.

Compute Operations(256 binary values)add()mul()sigmoid()relu()Geometric compute space(finite torus representation)
Torus wireframe
Atlas Framework
Byte-levelbijective mappingHash tableO(1) lookupClass Maps(96 bytes each)

Canonicalization and Optimization

Redundant operations are eliminated through algebraic simplification. Operation chains are fused, producing a compact representation.

Result: Typically 75% fewer operations after optimization.
Before Optimization12 operationsadd()+0mul()*1tanh()relu()sigmoid()norm()scale()add()mul()relu()After Optimization3 operationstanh + relu + sigmoidnorm + scaleadd + mul + relu(fused)75% Reduction12 → 3 operations

Circuit Generation

From the optimized representation, Hologram generates a fixed software-defined circuit using precomputed mappings over a finite torus, enabling predictable constant-time execution. This mirrors analog, quantum or FPGA-style fixed circuits, but runs as in-memory software on commodity hardware.

Optimized Operationsfused_op1fused_op2fused_op3Compile& FuseCircuitGenerationPrecomputedmappingsFinite TorusFreezeTopologySoftware-Defined CircuitFixed TopologyO(1) Deterministic ExecutionClassMap (96)ISAProgramMetadataNo branching • No runtime decisionsGeneral-purposeLossless encodingSoftware-defined

Comparison with

Analog Circuits
Computation flows through fixed geometric mappings rather than stepwise control flow, while remaining fully digital, deterministic, and noise-free.
Quantum Circuits
Multiple operations are mathematically fused into a single executable structure, achieving superposition-like efficiency without probabilistic behavior or specialized hardware.
FPGA Circuits
Execution uses a compile-time–fixed topology with predictable, constant-time behavior, delivered as software rather than reconfigurable silicon.

Binary Embedding

Hologram circuits compile to a backend agnostic ISA and embed directly into your application binary. This adds a small, bounded size increase (about 100 to 500 KB) and eliminates all runtime compilation, JIT, and loading overhead.

Mathematically Fast Runtime
Circuits are fully compiled at build time. At runtime there is minimal work to load, interpret, or warm up execution starts quickly and remains highly optimized.
Single-Binary Deployment
Circuits ship with your application as part of the executable. No sidecar files, no runtime dependencies, no environment-specific configuration.
Predictable Backend Plan
Execution plan headers grow linearly with computation complexity, reducing runtime complexity and improving startup time and reliability.

2. Run Anywhere

Hologram runs in-process as a library-level hypervisor, virtualizing execution across hardware backends.

In-Process Execution

Hologram executes entirely inside your application process. Circuits run in the same PID and memory space as your code, with no separate service, daemon, or runtime. There is no IPC and no network hop. Execution is direct function calls and memory access only.

Application Process(single PID)Application Code(your business logic)Hologram Runtime(execution engine)Embedded CircuitsISA programsClass mapsMetadataDirect function callsand shared memory accessNot requiredExternal serviceDaemon or sidecarIPCNetwork hop

Backend Abstraction

The backend layer takes precompiled, backend-agnostic ISA and executes it using hardware-specific implementations selected at runtime. A single compiled binary can run on CPUs, GPUs, or in the browser, with backend selection handled automatically and no environment-specific builds.

Hardware backend-agnostic

CPU

SIMD-optimized with Rayon parallelism. ~500ns for 1024 elements.

GPU

CUDA, Metal, WebGPU. ~10-50µs for 1024 elements.

WASM

SIMD128 in linear memory. ~1-2µs for 1024 elements.

Language Bindings

Use Hologram from your preferred language. UniFFI generates type-safe bindings automatically from the Rust core.

Python
from hologram import Executor, BackendType

exec = Executor.new(BackendType.CUDA)
buf = exec.allocate_f32(1024)
buf.copy_from([1.0] * 1024)
exec.run(circuit)

AI Framework Integration

Hologram works with open AI formats like ONNX and GGUF. Train in PyTorch or TensorFlow, export to ONNX, then compile into a fixed circuit optimized for inference, delivering near-instant AI on any device.

Train

PyTorch or TensorFlow

Export

Framework-agnostic ONNX

Compile & Deploy

Run near-instant AI inference on any device

3. Execute in Constant Time

Inputs flow through the circuit in a single pass. Operation chains collapse into fixed-cost primitives.

Single-Pass Execution

Hologram processes data in a single pass through a precompiled circuit. Operations are fused at build time, eliminating intermediate buffers, repeated passes, and redundant computation. Each element is read once and written once, delivering constant-time execution with predictable latency and minimal memory overhead.

Traditional Multi-Pass Execution
Input
Ops 1 (tanh)
Intermediate Buffer (DRAM)
Ops 2 (relu)
Intermediate Buffer (DRAM)
Ops 3 (sigmoid)
Output
Multiple passes over data
Intermediate buffers in DRAM
Repeated memory reads and writes

Cost: O(n) passes

Hologram Single-Pass Execution
Input
Precompiled Fused Circuit
Single hash table lookup
Compiled once
Output
Single pass through data
No intermediate buffers
Constant-time per element

Cost: O(1) per element

Fixed-Cost Primitives

Hologram delivers O(1) execution per element, independent of operation count or problem complexity, by fusing element-wise chains at compile time into a single 96-byte lookup table. Runtime execution becomes one cache-resident lookup and one memory pass, with no intermediate buffers, branching, or runtime computation.

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Cache-Optimized Memory Access

Hologram keeps hot execution data in CPU cache, with 96 byte class maps in L1 and ~1 KB ISA programs in L2. Runtime reduces to cache hits plus a single sequential input and output DRAM memory pass, delivering predictable low latency execution.

Processor Core
ISA Dispatch · Direct Memory Access
L1 Cache
Fused Class Map [96 bytes]
L2 Cache
Precompiled ISA Program [~1 KB]
System Bus
Single hash table lookup
DRAM
Input · Output (no operation code)

Performance Characteristics

Topology-dependent
Cost depends on circuit structure, not model size
Predictable execution
Bounded time, no worst cases
Stable performance
Same topology = same execution time
Performance Metrics

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Summary

Hologram transforms byte-level iterative computation into
fused circuit in-memory lookup that execute in constant time O(1).

Compile once
All optimization at build time.
Run anywhere
CPU, GPU, WASM, etc.
Execute with O(1) lookup
Single-pass runtime execution.